A novel high-speed bit-parallel multiply-accumulate arithmetic architecture employing mixed SB/TC number arithmetic

摘要

This paper presents an architecture for high-speed bit-parallel multiply-accumulate (MAC) arithmetic operation. This architecture employs the modified-Booth recoding algorithm for multiplication, and a kernel using mixed (sign, value)-encoded signed-binary (SB) and two's complement (TC) computation for carry-free generation of the SB partial-product sums. The final SB partial-product sum undergoes full-precision accumulation, rounding and overflow correction concurrently to facilitate a high-speed overall operation. A high-performance architecture is proposed for IEEE Standard 754 default rounding of the SB result. This architecture exploits the modified-Booth multiplication algorithm to generate the SIGN and STICKY indicators concurrently with the partial-product sum generation, and the carry-free property of redundant number addition to perform the final rounding operation concurrently with the accumulation operation. The conversion of the final rounded SB number into its corresponding TC format is achieved by using a fast pipelined lookahead converter. It is demonstrated that the use of (sign, value)-encoding leads to combined area- and time-efficient implementations. The resulting MAC arithmetic architecture is parameterized at the gate level and is subsequently verified using Viewlogic simulations for a corresponding 8 × 8 + 15 Actel 1.2-μm technology implementation.