Synthesis Techniques and Analysis Tool for On-Chip Fault-Tolerance

摘要

This report summarizes significant research on a broad range of issues related tofault-tolerant design both at the chip and system level. First discussed is an integrated approach, currently under development for integrating concurrent checking with BIST. The goal here is to generate synthesis tools to develop low cost fault-tolerant VLSI chip design tools that are both easy to test as well as being robust against operational errors. Section 2 reviews REACT, a tool currently under development for fault-tolerant architecture characterization. Finally, Section 3 presents on-going research on the development of novel fault-tolerant architectures.