Gate Level Simulator for Alpha-Particle-Induced Transient Faults

摘要

Mixed analog and digital mode simulators have been available for accurate alpha-particle-induced transient fault simulation. However, they are not fast enough to simulate a large number of transient faults on a relatively large circuit in a reasonable amount of time. This thesis describes a fast transient fault simulator which can evaluate the effects of alpha-particle hits or single event upsets (SEUs) in CMOS standard cell based synchronous sequential VLSI circuits. The speed comes from approximating the initial analog effects with gate level models, as well as using an improved transient fault simulation algorithm in a hierarchy of simulators. The simulator is shown to be between four to five orders of magnitude faster than a very accurate circuit simulator at the expense of some accuracy and some limitations on the types of circuits simulatable. Using this simulator, benchmark circuits have been tested for their behavior under alpha-particle injections. The experiment show that the one bit flip model is not a good model for injecting faults in highly fault tolerant systems. The experiments also show that at the pin level, no simple model exists which can mimic the behavior of the circuit hit with the alpha particle. The simulator's usefulness is also shown in the development of a transient pulse tolerant D flip-flop (DFF). The tool is used to demonstrate the tradeoff between transient pulse tolerance and latch performance. Transient faults, Alpha-particle-induced, VLSI circuits, Speed.