Clock Distribution Scheme for Large RSFQ Circuits

摘要

A primary issue for maximizing the performance of large scale synchronous digitalsystems is the clock distribution scheme. We present a novel clocking scheme, developed specifically for RSFQ logic, which is based on the concurrent flow of clock and data. The scheme allows the circuit throughput to be independent of inter-cell connection delays and significantly reduces the dependence of the throughput on the clock-to-output delay of the cells. Concurrent flow clocking is particularly well suited for structured architectures, such as systolic arrays. The simulated maximum clock frequency of an RSFQ decimation digital filter currently under development at the University of Rochester can be as much as seven times higher using concurrent-flow clocking rather than the conventional (counterflow) clocking. However, this advantage is reduced to a factor of two because of present day fabrication process variations.