Design of Digital Phase Locked Sensor Loop for Paralleled Inverters

摘要

This paper focused on the principle of phase-locked loop (PLL), the modeling and parameter design were also introduced in detail. The traditional PLL which influenced on phase demodulation errors of inverters with no control interconnection were studied further. Meanwhile, this paper designed a digital phase-locked sensor loop (DPLL) based on DSP using the concept of digital phase-locking. The tracking of phase and frequency in paralleled inverter can be realized effectively and rapidly by using DPLL, and also the parallel operation of inverters with no interconnection is solved. Moreover, the simulation data of this method keep consistent with the phase, frequency and amplitude. At last, the efficiency of research work mentioned above has been shown by experiments and simulations.