Design and Implementation of Digital Phase Locked Loop for Single-Phase Grid-Tied PV Inverters

摘要

In this article, a synchronous rotating-frame based phase-locked loop (PLL) for a single-phase PV inverter control system is presented. Detailed PLL mathematical model and the digital implementation for a single-phase PV inverter system are presented. A practical solution for transport delay based orthogonal signal generation using first-in-first-out (FIFO) circular buffer is also discussed. Details of implementation for a real-time system using digital signal processor were also described. The performance of the developed PLL was experimentally verified on a developed single-phase PV inverter prototype.