Biasing scheme for low-voltage CMOS cascode current mirrors

摘要

A bias generation scheme for CMOS cascode current mirrors is proposed. The bias voltage generated is equal to the sum of the overdrive voltage of the mirroring transistor and the gate source voltage of the cascode transistor. The proposed scheme is designed in a 65 nm n-well CMOS process with 1.8V supply and simulation results are provided for different process corners. The proposed idea is also found in the patent [1].