DESIGN AND IMPLEMENTATION OF A MINIATURIZED HIGH-LINEARITY 3-5 GHz ULTRAWIDEBAND CMOS LOW-NOISE AMPLIFIER

摘要

In this article, we demonstrate a miniaturized high-linearity (IIP3 = 8 dBm at 4 GHz) 3-5-GHz ultrawideband low-noise amplifier (LNA) implemented in a standard 0.18-μm CMOS technology. The inductive-series peaking technique was used to enhance the gain and bandwidth performances of the LNA. The measurement results show voltage gain greater than 10 dB, reverse isolation (S12) lower than -15 dB, and noise figure lower than 3.3 dB were achieved for frequencies lower than 5 GHz. In addition, input return loss (S11) lower than -8 dB was achieved for frequencies lower than 4.5 GHz. The chip area is only 0.4 mm{sup}2, excluding the test pads. This LNA drains 8.75 mA current at supply voltage of 2 V, i.e., it only consumes 17.5 mW power. These results are helpful for RFIC designers to realize miniaturized high-linearity RF receiver front-end ICs.