Technique for Large Elevation of Source/Drain Using Implantation Mediated Selective Etching

摘要

A process involving implantation mediated selective etching has been developed for source/drain elevation of metal-oxide-semiconductor devices. A 100 nm thick epitaxial silicon/polysilicon layer was formed on a patterned Si/SiO_2 structure by chemical vapor deposition (CVD) at 700 deg C. Samples were then implanted with 2 X 10~(14)/cm~2 argon at 140 keV in the <100> channeling direction, followed by 1 min annealing at 420 deg C. The polysilicon layer was then removed by wet etching with more than an order of magnitude selectivity over epitaxial silicon. The resulting structure of elevated silicon is free from faceting effects. The process is independent of sidewall/isolation materials, and not bound by thickness limits.