Semiconductor devices are becoming increasingly complex in terms of transistor count, frequency and integration. The distance between transistors is scaling down. The adoption of nanometer processes results in the new classes of defects that affect signal timing. The defect spectrum now includes more problems such as high impedance shorts, in-line resistance, and crosstalk between signals, which are not always detected with the traditional static-based tests, known as stuck-at tests. Detecting these delay defects requires a test approach that can apply test patterns at the rated speed of the device under test. Test generation is being developed in two directions. The usual trend is when the test is generated for the circuit at the structural level. In this case, the main problem is the test generation time, because it directly influences the time-to-market. The task of test generation is quite complicated, especially for sequential circuits. Therefore, the technique of design for testability (DFT) is applied during the design of such circuits. This helps to reduce the cost of test development. But the scan design allows a synchronous sequential circuit to be brought into the states that the circuit cannot visit during functional operation. As a result, it allows the circuit to be tested using test patterns that are not applicable during functional operation. This leads to unnecessary yield loss. The other disadvantage of DFT approach is that it adds extra delay to the circuit. The other important direction of test generation is the functional test development at the high level of abstraction. In the initial stages of the design, the structural implementation of the design is not known. Therefore the task of the test generation is more complex, because the test has to be generated for all the possible implementations. But the test development can be accomplished in parallel with other design stages. In this case, the time of test generation is not a critical issue. During design process, the software prototype of the circuit is created according to the specification. The software prototype simulates the functions of the circuit, enables to calculate the output values according to the input values. The functional test can be generated on the base of the software prototype. The functional test is very valuable also for the testing of intellectual property (IP) components whose implementation details are not known to the designer of the system on a chip. The size of a functional test is usually much larger than that of an implementation-dependent one to assure good fault coverage for many implementations. When the synthesis of a high level description into a particular implementation is completed, the minimization of the functional test according to the particular implementation can be provided in order to exclude the test patterns that do not detect the faults of the particular implementation. Next, the list of undetected faults can be formed, and the deterministic methods can be used to detect the faults from this list. The adaptation of the functional test according to the particular implementation is much simpler task than a generation of the test from the scratch. The process of adaptation doesn't require the long hours and it has a weak impact on the overall time of the design.
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