The study of dislocations in semiconductors parallels the development of the electronics industry. These silicon bulk defects commonly affect device technology due to many sources of variation from physical and manufacturing processes.[1] Continual quality improvements combined with constant economic pressure require a reduction in the number of these defects, which result in wafer fab manufacturing yield loss qualification failures or customer returns. Upstream from this long-term goal, the first requirement is to better understand and categorize the defect's effect in order to implement corrective actions. In this strategy, the failure analysis (FA) process must overcome traditional limits in terms of efficiency, responsiveness, and the technical methods used. This paper presents case studies of silicon pipeline defects (called "pipeline") and dislocations found on mixed-mode technology. Pipeline defects are specific dislocations that are widely reported to occur in CMOS and BiCMOS devices[2,3] and recently in silicon-on-insulator devices; the main distinction is that pipeline defects are considered to connect the source and drain regions of an NMOS transistor by diffusion of n-type dopants.
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