The failure analysis of dynamic random access memory (DRAM) follows a three-step process of electrical test and diagnosis, localization, and physical failure analysis. The electrical test delivers pass and fail results that are graphically displayed in bitmaps. The diagnosis of the bitmap results provides localization due to known layout data. The resolution of the localization depends on the analyzed layout elements. The limits of the bitmapping technique are reviewed and possible solutions by thermally-induced voltage alteration (TIVA), optical beam induced resistance change (OBIRCH), and soft defect localization (SDL) for failures in the devices' periphery of the array are discussed. The SDL technique may require an adaptation to memory test systems in order to provide high-speed comparison, allowing SDL image acquisition times of a few minutes. This article summarizes the contents of articles from the International Symposium for Testing and Failure Analysis (ISTFA) and the 6th edition of the Microelectronics Failure Analysis Desk Reference.
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