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首页> 外文期刊>ECS Journal of Solid State Science and Technology >Discrete Study of ALD TaN on Via and Line for Low Resistive and High Reliable Cu/Low-k Interconnects and Other Applications
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Discrete Study of ALD TaN on Via and Line for Low Resistive and High Reliable Cu/Low-k Interconnects and Other Applications

机译:低电阻,高可靠性Cu / Low-k互连和其他应用的通孔和线路上ALD TaN的离散研究

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摘要

Atomic layer deposition (ALD) of TaN was intensively studied for barrier metal in Cu line and Cu via separately by utilizing single damascene (SD) structure. As a barrier metal for via, thin ALD TaN 0.7 nm is insufficient to suppress dissolution of Cu seed during electrochemical plating, resulting in poor filling property. While, thicker ALD TaN 2 nm formed high resistance layer at via bottom. Moderate thickness of ALD TaN 1 nm showed lower via resistance and longer EM lifetime than PVD TaN/Ta. Besides, 1 nm thick ALD TaN achieved comparable TDDB lifetime to PVD TaN/Ta due to excellent barrier property. On the other hand, a certain thickness of PVD Ta layer is required on ALD TaN for line structure to obtain requisite adhesion between barrier metal and Cu for good EM performance. However, thicker PVD Ta led to higher line resistance. PVD Ta 5 nm is ideal thickness on ALD TaN 1 nm to achieve low line resistance and long EM lifetime.
机译:利用单镶嵌(SD)结构,分别研究了TaN的原子层沉积(ALD)在Cu线和Cu中的势垒金属。作为通孔的阻挡金属,薄的ALD TaN 0.7 nm不足以抑制电化学电镀期间Cu晶种的溶解,从而导致较差的填充性能。同时,更厚的ALD TaN 2 nm形成在通孔底部的高电阻层。 ALD TaN 1 nm的中等厚度显示出比PVD TaN / Ta低的导通电阻和更长的EM寿命。此外,由于具有出色的阻隔性能,1 nm厚的ALD TaN的TDDB寿命可与PVD TaN / Ta相媲美。另一方面,对于线结构,ALD TaN上需要一定厚度的PVD Ta层,以使阻挡层金属和Cu之间具有必要的粘合性,以获得良好的EM性能。但是,较厚的PVD Ta导致较高的线路电阻。 PVD Ta 5 nm是ALD TaN 1 nm的理想厚度,以实现低线电阻和长EM寿命。

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