首页> 外文期刊>ECS Journal of Solid State Science and Technology >Characterization of Plasma Process-Induced Latent Defects in Surface and Interface Layer of Si Substrate
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Characterization of Plasma Process-Induced Latent Defects in Surface and Interface Layer of Si Substrate

机译:硅衬底表面和界面层中等离子体工艺诱发的潜在缺陷的表征

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Characterization of plasma-induced Si substrate damage is demonstrated using an electrical capacitance-voltage (C-V) technique customized for the nano-scale analysis. Low resistive Si wafers are exposed to an inductively coupled plasma (ICP) or a capacitively coupled plasma (CCP). We focus on the effects of plasma parameters and wet-etching processes on plasma-induced physical damage (PPD) analyses. The optical thicknesses of surface and interfacial layers (d(SL) and d(IL)) were characterized using spectroscopic ellipsometry (SE) and compared with the electrical oxide thicknesses (EOT) obtained by the C-V technique. In the case of as-damaged samples, the optical thickness d(SL) by SE is found to be smaller than the EOT by the C-V technique, while the sum of d(SL) and d(IL) was approximately equal to the EOT. A diluted hydrofluoric acid (DHF) wet-etch step is employed to address depth profile of defect density in damaged samples. We identify the latent defect density, d(SL), and d(IL) after the DHF wet-etch, which are indispensible for practical device performance designs. It is found that, although the average energy of incident ions ((E) over bar (ion)) is larger for the case of CCP, the latent defect density of CCP-damaged samples is smaller than that of ICP even after the wet-etching. This finding is in sharp contrast to previous pictures-the larger (E) over bar (ion) leads to the thicker damaged layer and the larger latent defect density. We propose a model for these conflicting results, where the profiles of defect density and the sensitivities of each analysis technique are taken into account. The present work highlights the importance of the nano-scale damage characterization using the C-V technique, allowing to understand the influence of latent defects and to enable better design of future electronic devices. (C) The Author(s) 2015. Published by ECS. This is an open access article distributed under the terms of the Creative Commons Attribution Non-Commercial No Derivatives 4.0 License (CC BY-NC-ND, http://creativecommons.org/licenses/by-nc-nd/4.0/), which permits non-commercial reuse, distribution, and reproduction in any medium, provided the original work is not changed in any way and is properly cited. For permission for commercial reuse, please email: oa@electrochem.org. All rights reserved.
机译:使用专为纳米级分析定制的电容电压(C-V)技术演示了等离子体诱导的Si衬底损坏的特征。低电阻Si晶片暴露于电感耦合等离子体(ICP)或电容耦合等离子体(CCP)。我们专注于等离子体参数和湿法蚀刻工艺对等离子体诱导的物理损伤(PPD)分析的影响。表面和界面层的光学厚度(d(SL)和d(IL))使用光谱椭圆仪(SE)进行表征,并与通过C-V技术获得的电氧化物厚度(EOT)进行比较。对于损坏的样品,通过CV技术发现SE的光学厚度d(SL)小于EOT,而d(SL)和d(IL)的总和大约等于EOT 。采用稀释的氢氟酸(DHF)湿法蚀刻步骤来解决受损样品中缺陷密度的深度分布。我们确定了DHF湿法刻蚀后的潜在缺陷密度d(SL)和d(IL),这对于实际的器件性能设计是必不可少的。结果发现,尽管对于CCP而言,入射离子的平均能量((E)超过bar(离子))更大,但即使在湿法湿法腐蚀后,CCP损坏样品的潜在缺陷密度也比ICP小。蚀刻。这一发现与先前的图片形成鲜明的对比-较大的(E)条形图(离子)导致损坏的层更厚,潜在的缺陷密度更大。我们针对这些矛盾的结果提出了一个模型,其中考虑了每种分析技术的缺陷密度和灵敏度。本工作强调了使用C-V技术表征纳米级损伤的重要性,这有助于了解潜在缺陷的影响并能够更好地设计未来的电子设备。 (C)2015年作者。ECS发布。这是根据知识共享署名非商业性非衍生产品4.0许可(CC BY-NC-ND,http://creativecommons.org/licenses/by-nc-nd/4.0/)的条款分发的开放获取文章,只要原始作品不做任何改变并得到适当引用,就可以在任何媒体上进行非商业性的重用,发行和复制。要获得商业重用的许可,请发送电子邮件至:oa@electrochem.org。版权所有。

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