16-NM MULTIGATE AND MULTIFIN MOSFET DEVICES AND SRAM CIRCUITS

摘要

In this work, we explore the effect of the number of fins and fin structure on the DC and dynamic behaviors of multigate and multifin field effect transistor (FET) circuits including random-dopant- and workfunction-induced characteristic fluctuations. Multifin FETs with different fin aspect ratios [AR = fin height (H_(fin))/fin width (W_(fin))] and a fixed channel volume are simulated using an experimentally validated three-dimensional device simulation. The multifin FinFET (AR = 2) has better channel controllability and drivability than the multifin trigate (AR =1) and multifin quasi-planar (AR = 0.5) FETs. Although FinFETs have a large effective device width and driving current, their large gate capacitance limits gate delay. The transient characteristics of an inverter with multifin transistors are further examined and compared with those of an inverter with single-fin transistors. The multifin inverter has a shorter delay because it is dominated by the driving current of the transistor. A six-transistor static random access memory (6T SRAM) using multifin FinFETs provides the largest static noise margin (SNM) because it supports the highest transconductance in FinFETs. With respect to random-dopant- and workfunction-induced fluctuations, the multifin FinFET suppresses not only the potential barrier's variation but also DC characteristic fluctuations because it has a more uniform surface potential than the multifin trigate and quasi-planar FET, and so the effects of random dopants and workfunction on the 6T SRAM could be minimized. Further, the SNM fluctuation can be suppressed by 8T SRAM, especially for FinFET-shaped fin. The results of this study provide insight into the DC and SRAM circuit's characteristics of multigate and multifin transistors and associated random dopant fluctuations.