Design of Low Power Optimized MixColumn/Inverse MixColumn Architecture for AES

摘要

Information security has become an important issue in the modern world. To ensure secure communication in the field of information, various cryptography algorithms have been used. Advanced Encryption standard is one of the most popular security algorithms. Power reduction and compact size are playing vital role in the security based application design, especially smart card application. In this paper, we proposed low power architectural model of MixColumn Transformation which is part of the Advanced Encryption Standard. Generally, MixColumn Transformation requires matrix multiplication which takes more number of gates, in both encryption and decryption operation. The forward MixColumn Transformation is used in Encryption operation where as inverse Mix Column Transformation is used in decryption process. In this paper, analysis of optimized power and area model Mix Column Transformation based on Galois Field model is done. The proposed Mix Column Transformation architecture has been analyzed with the help of the Galois finite field, which is tower field Advanced Encryption Standard model. For this implementation, we have used Xilinx 14.1 synthesis tool, Xpower analyzer for analyze the gate count and power model. The proposed model can be implemented in Xilinx SPARATN 3E device.