An architectural design of SubBytes and Mixcolumns for AES cryptography

摘要

In recent years, security of DES is decreasing according to the progress of network technology as well as computer science. As a result, MST carried out the standardization of AES and decided Rijndael for AES last year. In this paper, we designed SubBytes and MixColumns transformation in various ways to realize an AES hardware system on a FPGA chip. Their performance is evaluated through their speed and circuit size.