We propose a sense scheme that a pMOS charge-transfer maintains bit-line level near the GND level when the plate-line goes high. The scheme supplies 0.5 V higher read-out voltages across the cell capacitors and enables a 0.4 V higher differential amplitude in a 51w-cell per bit-line structure than conventional DRAM sense scheme. A Shifted bias Plate Line layout enables 8 cells and 8 sense amplifiers activation in a cell mat that achieves 8.06 mW @ 3 V, 5 MHz by simulation, about same as conventional device.
展开▼
