Recoding input sets of a combinational circuit in FPGA-based design

摘要

A method of recoding specified input sets of a combinational circuit that had been designed on the basis of field programmable gate arrays (FPGA) is considered. The method is based on construction of a code the variables of which are functions of a subset of input variables, and, moreover, distinguish any pair of input sets that generate distinct output sets. By means of the method, it is possible to take into account constraints on the number of input poles of the logical blocks occurring in an FPGA structure.