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Detector circuit for electrical circuit, has flip-flop circuit provided as reset-set-latch and comprising reset-input, set-input and output nodes, where latch has seven transistors that are connected with one another
Detector circuit for electrical circuit, has flip-flop circuit provided as reset-set-latch and comprising reset-input, set-input and output nodes, where latch has seven transistors that are connected with one another
The circuit has a flip-flop circuit comprising two states and provided as a reset-set-latch. The flip-flop circuit has a reset-input (R), set-input (T) and output nodes (Z, ZN), where the latch has seven transistors that are connected with one another. A gate-connection and a source connection of one of transistors are connected with the set-input and the reset-input, respectively. An inverter is connected upstream of the reset-input and another inverter is connected downstream of an output. Independent claims are also included for the following: (1) a circuit arrangement comprising detector circuits (2) a method for operating a circuit arrangement.
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