Ni (10%Pt) Silicide Processes For 22 nm CMOS Technology and Beyond

摘要

In this paper 10% Pt in the Ni(Pt) silicide was studied. The sheet resistance results indicate that the treatment, RTA1 at 310℃ for 60S and RTA2 at 480℃ for 10S, can form the minimum sheet resistance, preferable Rs Std.Dev and thickness uniformity. With Pt addition, Ni(Pt)Si/Si morphology is stable with temperature rising until 700℃. There is NiSi spike for optimal silicidation of 2nm Ni(5%Pt) film. However, the optimal silicidation of 2nm Ni(10%Pt) film has a smooth Ni(Pt)Si/Si interface and better uniformity. The effect of Ar clean on sheet resistance and thickness uniformity is also investigated. The results show that wafers after wiping out surface oxide in less than one hour without Ar clean process have the reduction about 10%~40% in sheet resistance, comparing with wafers with Ar clean. Ni(10%Pt) silicide is tested and verified at 0.5μm and 22nm structure. It has a good interface and uniformity without any spike.