A 14.8 ps jitter low-power dual band all digital PLL with reconfigurable DCO and time-interlined multiplexers

摘要

Using recently the developed dual band digitally controlled oscillator, in this paper, it can be proposed a low-power dual band all digital PLL (ADPLL). In the proposed ADPLL, toggling the input control bit utilizes the ADPLL to switch between two special frequency bands. An additional control circuit is also employed to have reasonable linearity. Sustaining coarse and fine characteristics and with a blend of capacitive shift and Schmitt trigger techniques, this oscillator changes the trigger points of the circuit and thus results in changeable delay and therefore, in creation of two different frequency bands. If the multiples of these bands used, it can cover two different frequency bands with one input toggling situation. It can be utilized in situation when it switched between two different frequencies for two unlike application or multi-standard bands. In such an occasion, instead of using two ADPLLs, the proposed structure, which decreases the needed area, can be used. Moreover, in this method, there is no need for redesigning and appraising the degree of stability against voltage changes, temperature and process of two ADPLLs. Simulation of the proposed dual band ADPLL is performed with Hspice by a voltage of VDD = 1.8v in 180 nm CMOS technology. The frequency range of the proposed dual band digitally controlled oscillator is from 97.18 to 117.65 MHz in lower band and 134.05-177.03 MHz in the high band.