An integrated method of timing-driven floorplanning and behavioral synthesis

摘要

In deep submicron semiconductor technology, interconnection becomes the most dominant factor of system performance. Thus in the early step of VLSI design, the design technique considering interconnection among modules as well as floorplanning is needed. In this paper, we focus on a control data flow graph (CDFG) including conditional branches, and effectively handle resource sharing based on exclusiveness of conditional branches. We propose a behavioral synthesis method consisting of scheduling, allocation, and binding, with the prediction of a final layout. The proposed method searches only the space which satisfies design constraints of chip area and clock frequency in a huge design space by performing a more exact wiring delay estimation.