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An integrated method of timing-driven floorplanning and behavioral synthesis

机译:时序驱动的布局和行为综合的集成方法

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摘要

In deep submicron semiconductor technology, interconnection becomes the most dominant factor of system performance. Thus in the early step of VLSI design, the design technique considering interconnection among modules as well as floorplanning is needed. In this paper, we focus on a control data flow graph (CDFG) including conditional branches, and effectively handle resource sharing based on exclusiveness of conditional branches. We propose a behavioral synthesis method consisting of scheduling, allocation, and binding, with the prediction of a final layout. The proposed method searches only the space which satisfies design constraints of chip area and clock frequency in a huge design space by performing a more exact wiring delay estimation.
机译:在深亚微米半导体技术中,互连成为系统性能的最主要因素。因此,在VLSI设计的早期阶段,需要考虑模块之间的互连以及布局规划的设计技术。在本文中,我们专注于包含条件分支的控制数据流图(CDFG),并基于条件分支的排他性有效地处理资源共享。我们提出一种行为综合方法,包括调度,分配和绑定,并预测最终布局。所提出的方法通过执行更精确的布线延迟估计,仅在巨大的设计空间中搜索满足芯片面积和时钟频率的设计约束的空间。

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