Analysis of a high performance self-aligned elevated source drain MOSFET with reduced gate-induced drain-leakage

摘要

A novel self-aligned ESD (Elevated Source Drain) MOSFET structure which can effectively reduce the GIDL (Gate-Induced Drain Leakage) current is proposed and analyzed. The proposed FSD structure is characterized by sidewall spacer width and recessed-channel depth which are determined by dry-etching process. Elevation of the Source/Drain extension region is realized so that the low-activation effect caused by low-energy ion implantation can be avoided. Unlike the conventional LDD structures, it is shown that the GIDL current of the ESD structure is suppressed without sacrificing the maximum driving capability. The main reason for the reduction of GIDL current is the decreased electric field at the point of the maximum band-to-band tunneling as the peak electric field is shifted toward the drain side.