Proposal and analysis of novel non-volatile ferroelectric latch circuit for low operation voltage

摘要

Aiming for the realization of latch circuits with full Multiple-Threshold CMOS Technology, a novel circuit configuration of non-volatile latch circuit with ferroelectric-gate field effect transistors is proposed. SPICE analysis of conventional and newly proposed ferroelectric latch circuits with 1V power supply is performed. The result suggests that the probability of failure operation for a conventional ferroelectric latch circuit is higher than that for newly proposed one which has high speed and stable data restoring feature.