Non-volatile latch with low voltage operation

摘要

Methods, circuits, devices, and/or arrangements for providing a non-volatile latch are disclosed. In one embodiment, a non-volatile latch can include: (i) a first non-volatile memory (NVM) cell coupled to a first supply, a first gate (e.g., a control gate), and an output node, where the first NVM cell is configured to be in a first state; and (ii) a second NVM cell coupled to a second supply, a second gate (e.g., another control gate), and the output node, where the second NVM cell is configured to be in a second state.