Analysis of power dissipation due to short-circuit current in CMOS logic circuits

摘要

A purpose of this paper is to establish a technique that can easily calculate power dissipation of logic Circuits due to a direct-path short-circuit current. Characteristics of the short-circuit power dissipation (P{sub}s) of an inverter have first been examined. It was found that P5 was a function of both rise- and fall-times (t) of an input voltage and an output load-capacitor (C). It was difficult to estimate both t and C for an individual single gate in a large circuitry 50 we have developed a simple P{sub}s expression of the inverter as a function of the number of logic gates parallel to this inverter and the number of fun-outs, instead of using t and C. P{sub}s expressions for other logic gates such as NANDs, NORs, etc. will be established so we could easily estimate P{sub}s of logic circuitries without using CAD tools.