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首页> 外文期刊>Journal of instrumentation: an IOP and SISSA journal >Design and standalone characterisation of a capacitively coupled HV-CMOS sensor chip for the CLIC vertex detector
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Design and standalone characterisation of a capacitively coupled HV-CMOS sensor chip for the CLIC vertex detector

机译:CLIC顶点检测器的电容耦合HV-CMOS传感器芯片的设计与独立特征

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摘要

The concept of capacitive coupling between sensors and readout chips is under study for the vertex detector at the proposed high-energy CLIC electron positron collider. The CLICpix Capacitively Coupled Pixel Detector (C3PD) is an active High-Voltage CMOS sensor, designed to be capacitively coupled to the CLICpix2 readout chip. The chip is implemented in a commercial 180 nm HV-CMOS process and contains a matrix of 128 × 128 square pixels with 25 μm pitch. First prototypes have been produced with a standard resistivity of ~ 20 Ω cm for the substrate and tested in standalone mode. The results show a rise time of ~ 20 ns, charge gain of 190 mV/ke~ ? and ~ 40 e ~? RMS noise for a power consumption of 4.8 μW/pixel. The main design aspects, as well as standalone measurement results, are presented.
机译:在所提出的高能Clic电子正电子共源撞机处,在Vertex探测器之间研究了传感器和读数芯片之间的电容耦合的概念。 电容耦合像素检测器(C3PD)的CLICPIX是一个有源高压CMOS传感器,设计用于电容耦合到CLICPIX2读数芯片。 该芯片在商业180nm HV-CMOS过程中实现,并包含具有25μm间距的128×128平方像素的矩阵。 已经生产了第一种原型,标准电阻率为〜20Ωcm的基板,并在独立模式下进行测试。 结果表明〜20 ns的上升时间,电荷增益为190 mV / ke〜? 〜40 e〜? RMS噪声为4.8μW/像素的功耗。 主要设计方面以及独立的测量结果呈现。

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