A New Physical Design Approach for Setup Timing Optimization in 7 nm Global Routed Designs

摘要

The scaling of semiconductor technologies to the atomic level has several important consequences on design performance. Today's System on Chips (SoCs) may operate in several Gigahertz (GHz) frequency. Particularly for 7 nm technology that offers more speeds compared to 10, 14 and 16 nm nodes with higher density, a greater number of I/OS and more metal layers (routing capability improvement). With all these technology advancements, new challenges have raised, one of these challenges is the interconnect domination of the overall circuit's performance, this new physical constraint should be taken into consideration as early as possible in the design development cycle to achieve design timing closure. In this study, we aim to close timing by reducing net delays using layer optimization during global routing. The idea is to use the difference in 7 nm metal layers electrical properties to meet its timing requirements. The method effectively optimizes timing in nets by faithfully decreasing the effective resistance and the coupling capacitance between wires. By the end of this research, we will propose a complete algorithm for timing closure in a 7 nm scale design. This approach has been shown to be effective with a gain of 35.5% in the Worst Negative Slack (WNS), 26.66% in the Total Negative Slack (TNS), 4.29% in the Total Hold Slack (THS) and 17.91% m the Worst Hold Slack (WHS) respectively, compared to the baseline flow.