Programmable Truncated Multiplier

摘要

Multipliers are the major units in any signal processing applications. Truncated multiplication scales down the power required by multipliers by only measuring the most-significant bits of the output. The most common approach in truncation includes physical reduction of the partialproduct matrix and a compensation for the reduced bits via different hardware compensation sub circuitry. However, this result in fixed systems optimized for a given application at design time. In this paper, a simple approach towards truncation is proposed, where a full precision multiplierwith an error tolerant adder is implemented, whose active selection of the partial product matrix is done instantly at run-time. Experimental results including power measurements are studied.