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首页> 外文期刊>American journal of applied sciences >Field Programmable Gate Arrays Based Realization of Truncated Multipliers | Science Publications
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Field Programmable Gate Arrays Based Realization of Truncated Multipliers | Science Publications

机译:基于现场可编程门阵列的截断乘法器的实现科学出版物

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摘要

> Problem statement: Due to high cost and non reconfiguration of Application Specific Integrated Circuits (ASICs) in image processing applications, for example MPEG video compression used in CT scan frames requires real time conditions and the algorithms should be verified and optimized before implementation. Approach: Field Programmable Gate Array (FPGA) provides reconfiguration and implementation at the same time. Results: The implementation results of truncated multipliers on Sparatn-3An FPGA showed significant improvement as compared to Virtex and Virtex-E FPGA devices. Conclusion: Truncated multipliers can be used in medical imaging technology such as CT scan.
机译: > 问题陈述:由于成本高且图像处理应用中的专用集成电路(ASIC)无法重新配置,例如CT扫描帧中使用的MPEG视频压缩需要实时条件和算法应在实施之前进行验证和优化。 方法:现场可编程门阵列(FPGA)同时提供重新配置和实施。 结果:在Sparatn-3上,截断乘法器的实现结果与Virtex和Virtex-E FPGA器件相比,显示出显着的改进。 结论:截断乘法器可用于医学成像技术,例如CT扫描。

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