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首页> 外文期刊>Trends in Ecology & Evolution >A Discrete-Time Frequency-Locked Loop for Single-Phase Grid Synchronization Under Harmonic Distortion
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A Discrete-Time Frequency-Locked Loop for Single-Phase Grid Synchronization Under Harmonic Distortion

机译:在谐波失真下的单相网平衡的离散时间锁定环路

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摘要

This article presents a discrete-time frequency-locked-loop (FLL) scheme that estimates the in-phase fundamental component of a distorted single-phase reference signal and its fundamental angular frequency. The proposed scheme also estimates the square-phase fundamental component as a set of orthogonal signals. The proposed design is based on an exact discrete model of a single-phase signal generator. It is shown that the proposed method provides an accurate response even under low sampling frequency. The proposed scheme includes, as a plug-in block, an explicit harmonic compensation mechanism to reduce the effect of harmonic distortion. The article includes a local stability analysis for the proposed scheme as well as guidelines for control parameter tuning. Experimental results are provided to assess the performance of the proposed scheme under angular frequency variations and harmonic distortion on the reference signal.
机译:本文介绍了一种离散时间锁相环(FLL)方案,估计失真的单相参考信号的相位基本组件及其基本角频率。 该拟议方案还估计平方相基本组件作为一组正交信号。 所提出的设计基于单相信号发生器的精确离散模型。 结果表明,即使在低采样频率下,所提出的方法也提供了准确的响应。 该提出的方案包括作为插件块,是一种明确的谐波补偿机制,以降低谐波失真的影响。 该物品包括所提出的方案的局部稳定性分析以及控制参数调谐的指南。 提供了实验结果,以评估在角频变化和参考信号上的谐波失真下提出的方案的性能。

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