Device and circuit level analysis of negative capacitance hybrid CMOS: a prospect for low power/low voltage applications

摘要

In this work, a concept of negative capacitance hybrid CMOS (NCHCMOS) is presented which consists of p-NCGeOIFET (NC germanium-on-insulator FET) and n-NCSiGeOIFET (NC SiGe-on-insulator FET). Both devices have been simulated by using respective calibrated TCAD models with Landau-Khalatnikov equation. The enhanced performance of both devices due to NC effect has been shown in terms of improved barrier and subsequently reduced leakage current (by 2 orders). The max gain of Ge and SiGe NCFETs has been found to be 1.64 and 1.56 (i.e. >1) respectively which is manifested in reduced subthreshold swing values. Results have also shown that the NC of ferroelectric material attributes to very high gate capacitance which is further responsible for enormous increase in on-state current (170% in p-NCGeOIFET and 103% in n-NCSiGeOIFET). Further, to investigate the performance of these devices in low power/low voltage applications, static and transient characteristics of NCHCMOS based gates and circuit have been obtained. It has been shown that NCHCMOS gives improved circuit performance in terms of high noise margin, reduced rise and fall time, less propagation delay, and reduced power and energy dissipation as compared to HCMOS. It is also displayed that NCHCMOS exhibits very less values (approximately by an order or 2) of energy-delay-product in respect to HCMOS and provides energy efficient operation.