Optimization of the Bond and Etch-Back Silicon-on-lnsulator Manufacturing Processes

摘要

We have studied the bond and etch-back silicon on insulator (BESOI) manufacturing processes. The top silicon layer, called device layer, was studied from its epitaxial growth on 2 μm thick SiGeB etch-stop layer, through 850 ℃/12 h bond strengthening annealing and selective etching, to the final chemical-mechanical planarization (CMP) treatment. We have found that the device layer thickness is reduced during the annealing and selective tetramethylamonium hydroxide and HNA (mixture of hydrofluoric, nitric and acetic acids) etching processes. This thickness reduction was found to be 0.592 μm, independently on the original device layer thickness. We have also found that the wafer surface is covered by a thin silicon suboxide layer after the HNA etching. The layer can be however easily removed by CMP with stock removal higher than 0.1 μm. Such process also polishes the wafer surface to prime quality micro-roughness. For studied BESOI process we therefore propose additional epitaxial growth of 0.8 μm to the thickness target of the lightly doped epitaxial layer (future device layer) and using CMP stock removal of 0.2 μm to obtain BESOI wafer with superior device layer surface micro-roughness and thickness uniformity.