Verification IP for AMBA AXI Protocol using System Verilog

摘要

The growth of CMOS technologies has increased the design of more complex digital systems using reusable IP's. This lead to the process of functional verification more and more complex. In this scenario, the verification engineers come with an inbuilt verification environment called as verification IP (Intellectual Property) Cores to reduce the time span of verification and increase the functionality check accuracy. This verification environment accurately monitors and captures the functional errors for all the cases and makes the process of design/verification so easy. Hence in this research article, the Advanced Microcontroller Bus Architecture is designed and a verification environment for 100% functional verification is also proposed. In this verification methodology the individual modules of the AXI and verification environment are designed using System Verilog HDL and simulated using Mentor Graphics Questasim. In this verification scenario, the functionality is verified for five different test-cases and then with a code coverage enabled verification process. For all the verification test-cases the performance of the bus is assessed by the calculated values of Valid Count, Busy Count and Bus Utilization factor.