Synthesis and Verification of a GaAs Microprocessor from a Verilog HardwareDescription

摘要

The University of Michigan Gallium Arsenide MIPS Project is using Verilog in thedesign of a 250 MHz MIPS architecture microprocessor. The design system is based on a single Verilog model which is used for simulation, synthesis, and hardware verification. The model is composed of a mixture of Register Transfer Level (RTL) and behavioral descriptions. Datapaths are represented by RTL structural components, while the control logic has behavioral descriptions. To simplify verification and test development, a number of operating system functions have been implemented using the Verilog PLI (Programming Language Interface). These functions allow the model to load and execute programs compiled for the DECstation 5000. To ensure the model's functional correctness, a verification tool compares simulation results against the execution of an physical MIPS processor. Any inconsistencies are flagged as errors. Once the model is deemed functionally correct, it is synthesized into a logic level implementation. Datapath logic, described at the register transfer level, is directly mapped into a netlist for automatic placement and routing. The control logic is translated to the Finesse logic synthesis language. The Finesse compiler then synthesizes each control block into a netlist which is passed to the physical design tools from Cascade Design Automation (CDA) for final layout.