DLL Based Clock Generator with Low Power and High Speed Frequency Multiplier

摘要

An effective less power, and enhancement of frequency multiplier for a delay-locked loop clock generator is used to produce an increased frequency by multiplied clocks. Here edge combiner which we have used to enhance multiplied frequency gives more speed and effective operation is done as we use different structure and overlap canceller. On other hand by applying the logic that satisfies our requirement of pulse generator and multiplication-ratio control logic design, we reduces the delay difference between positive- and negative-edge of the generated pulse, which causes a known jitter which we called as deterministic jitter.