Low -noise local oscillator design techniques using a DLL-based frequency multiplier for wireless applications.

摘要

The fast growing demand of wireless communications for voice and data has driven recent efforts to dramatically increase the levels of integration in RF transceivers. One approach to this challenge is to implement all the RF functions in the low-cost CMOS technology, so that RF and baseband sections can be combined in a single chip. This in turn dictates an integrated CMOS implementation of the local oscillators with the same or even better phase noise performance than its discrete counterpart, generally a difficult task using conventional approaches with the available low-Q integrated inductors. This is a particularly severe problem in RF systems such as AMPS, where the channel spacing is small and close-in phase noise must be extremely low.;In this thesis the fundamental performance limit of a local oscillator design using a DLL-based frequency multiplier is investigated. The distinctive timing jitter accumulation pattern of a DLL-based frequency multiplier is analyzed in detail to predict the phase noise performance based on the thermal-noise-induced jitter of the source-coupled differential CMOS delay cell implementation. The result suggests an unique phase noise signature compared to a PLL approach using a VCO. Due to the limited timing jitter accumulation in a DLL, the close-in phase noise performance of the DLL-based frequency multiplier is much lower than that of a monolithic VCO.;The specific research contributions of this work include (1) proposing a new local oscillator architecture using a DLL-based frequency multiplier that breaks the traditional LO phase noise limitations, (2) an analytical model that describes the phase noise performance of the proposed local oscillator architecture, (3) the application of the DLL-based frequency multiplier to a monolithic CMOS low-phase-noise local oscillator for cellular telephone applications.;To demonstrate the proposed concept, a fully integrated CMOS local oscillator utilizing a DLL-based frequency multiplier technique to synthesize a 900MHz carrier with low close-in phase noise was designed. This prototype, implemented in a standard 0.35mum CMOS technology, achieves --123dBc/Hz phase noise at 60kHz offset while dissipating 130mW from a 3.3V supply, meeting the requirements of the IS-137 dual-mode standard.