Phase noise model of ring oscillator under reduced supply with application to a time to digital converter

摘要

This paper investigates the phase noise of voltage controlled ring oscillators. The delay cell is a differential pair with no tail current source, suitable for reduced supply voltage as technology scales. As N, number of stages, decreases, the output can become unsaturated, introducing extra correlation and adding phase noise. The new phase noise model is developed (focusing on N = 2), which improves on impulse sensitivity function, Using a 0.13 mu m CMOS technology in 1.2 V supply, this model is applied to the delay cell under different circuit parameters (focusing on tuning) and operating conditions, with theoretical results agreeing with simulations. The design was fabricated in 0.13 mu m CMOS, and operates at 0.89 GHz oscillator frequency, and has 200 mu W power consumption. To study the phase noise when the VCO is tuned, measurements at the boundary of typical tuning range is performed and agree with theory and simulations. Insights, based on theory, are presented and explain trends of simulated and measured phase noise. Next the ring oscillator is applied to a time to digital converter (TDC). Using the above noise model, the jitter of the VCO is calculated and then apply to calculate the resulting jitter in the TDC. Then the TDC is simulated with Matlab, with VCO jitter injected, and find reasonable comparison with theory.