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Facile Formation of Graphene P-N Junctions Using Self-Assembled Monolayers

机译:使用自组装单分子膜轻松形成石墨烯P-N结

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摘要

Monolithic and patterned aminopropyltriethoxysilane (APTES) layers are used to create n-doped graphene, graphene p-n junctions, and FET devices containing p-n junctions in the device channel through transfer of CVD graphene onto APTES coated substrates. APTES doping is shown to not result in introduction of defects. I-V measurements of FET devices containing patterned APTES layers show it is possible to control the position of the two current minima (two Dirac points) in the ambipolar p-n junction.
机译:整体和图案化的氨基丙基三乙氧基硅烷(APTES)层用于通过将CVD石墨烯转移到APTES涂覆的基板上来创建n掺杂的石墨烯,石墨烯p-n结,以及在器件通道中包含p-n结的FET器件。事实表明,掺杂APTES不会导致引入缺陷。包含图案化APTES层的FET器件的I-V测量表明,可以控制双极性p-n结中两个电流最小值(两个Dirac点)的位置。

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