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首页> 外文期刊>Nanotechnology >Control of metamorphic buffer structure and device performance of InxGa1-xAs epitaxial layers fabricated by metal organic chemical vapor deposition
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Control of metamorphic buffer structure and device performance of InxGa1-xAs epitaxial layers fabricated by metal organic chemical vapor deposition

机译:金属有机化学气相沉积制备的InxGa1-xAs外延层的变质缓冲结构和器件性能的控制

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Using a step-graded (SG) buffer structure via metal-organic chemical vapor deposition, we demonstrate a high suitability of In0.5Ga0.5As epitaxial layers on a GaAs substrate for electronic device application. Taking advantage of the technique's precise control, we were able to increase the number of SG layers to achieve a fairly low dislocation density (similar to 10(6)cm(-2)), while keeping each individual SG layer slightly exceeding the critical thickness (similar to 80 nm) for strain relaxation. This met the demanded but contradictory requirements, and even offered excellent scalability by lowering the whole buffer structure down to 2.3 mu m. This scalability overwhelmingly excels the forefront studies. The effects of the SG misfit strain on the crystal quality and surface morphology of In0.5Ga0.5As epitaxial layers were carefully investigated, and were correlated to threading dislocation (TD) blocking mechanisms. From microstructural analyses, TDs can be blocked effectively through self-annihilation reactions, or hindered randomly by misfit dislocation mechanisms. Growth conditions for avoiding phase separation were also explored and identified. The buffer-improved, high-quality In0.5Ga0.5As epitaxial layers enabled a high-performance, metal-oxide-semiconductor capacitor on a GaAs substrate. The devices displayed remarkable capacitance-voltage responses with small frequency dispersion. A promising interface trap density of 3 x 10(12) eV(-1) cm(-2) in a conductance test was also obtained. These electrical performances are competitive to those using lattice-coherent but pricey InGaAs/InP systems.
机译:通过金属有机化学气相沉积使用逐步分级(SG)缓冲结构,我们证明了In0.5Ga0.5As外延层在GaAs衬底上对于电子设备应用的高度适用性。利用该技术的精确控制,我们能够增加SG层的数量以实现相当低的位错密度(类似于10(6)cm(-2)),同时使每个单独的SG层略微超过临界厚度(类似于80 nm)进行应变松弛。这满足了要求但矛盾的要求,甚至通过将整个缓冲区结构降低到2.3μm而提供了出色的可伸缩性。这种可伸缩性绝对优于最前沿的研究。仔细研究了SG失配应变对In0.5Ga0.5As外延层晶体质量和表面形态的影响,并将其与螺纹位错(TD)阻断机理相关。从微观结构分析来看,可通过自reactions灭反应有效阻断TD,或通过失配位错机制随机阻止TD。还探索并确定了避免相分离的生长条件。经过缓冲改进的高质量In0.5Ga0.5As外延层使GaAs基板上的高性能金属氧化物半导体电容器成为可能。这些器件显示出出色的电容电压响应,且频率分散较小。在电导测试中也获得了有希望的界面陷阱密度为3 x 10(12)eV(-1)cm(-2)。这些电性能与使用晶格相干但价格昂贵的InGaAs / InP系统的产品相比具有竞争力。

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