A Full Scan Design Method for Asynchronous Sequential Circuits Based on C-element Scan Paths

摘要

Using asynchronous VLSI designs resolve synchronous circuit design difficulties, e.g. the clock skew, higher throughput and lower power consumption. ITRS predicts that a globally-asynchronous, locally-synchronous (GALS) design scheme will be adopted for various applications in near future. Although a full scan design method for synchronous circuits is applied to asynchronous circuits to achieve the same testability of their combinational parts, the overhead is extremely high. To reduce the overhead, several full scan design methods have been proposed but they cannot guarantee complete test. In this paper, we propose a bipartite full scan design as a new DFT method for asynchronous circuits where we guarantee complete test for both combinational and sequential parts of circuits with area and performance overhead comparable to the previous best method in terms of overhead.