Evaluation of impurity depletion effect near n{sup}+poly-Si gate side wall/SiO{sub}2 interfaces for sub-100nm nMOSFETs

摘要

2Oμm-3Onm gate length nMOSFETs with 1.6-1.86nm thick gate oxide have been fabricated, and the gate leakage current and the gate resistance have been studied systematically as a function of the gate length. It is found that, in the sub-O.5μm gate length region, the gate resistivity drastically increases with decreasing gate length. The result is interpreted in terms of the carrier depletion in poly-Si gate due to phosphorus pile-up at the gate poly-Si/SiO{sub}2 interface.