A Comprehensive Study of Punchthrough Characteristics in Multiple-Gate MOSFETs - The Trend of Punchthrough Voltages in Various Gate Shapes of SOI MOSFETs

摘要

Punchthrough characteristics are investigated for different gate structures on silicon-on-insulator (SOI) FinFET. The punchthrough voltage (V{sub}(PT)) was measured and verified by 3-D Silvaco simulator for various fin widths, crucial parameter to govern short-channel effects. The simulated results show a good agreement to the experimental data. Thereafter, the punchthrough voltages for multiple-gate structures in the SOI FinFETs: conventional FinFET, Π-gate FinFET, Ω-gate FinFET and all-around-gate FinFET, were simulated with the aid of the Silvaco simulator after verification with experimental data. When the overlapped area of the gate-channel straddling the body increases, leakage paths reduce, and the punchthrough voltages increase as a result. For aggressive device scaling, all-around gate is highly preferable.