A 1.0-V 12-bit Digitally Calibrated SAR ADC Using Hybrid DAC Technique

摘要

A 1.0-V, 12-bit, 80-MS/s two time-interleaved successive approximation register (SAR) ADC with 1.2-V differential full-scale voltage is presented. To minimize the circuit area, a hybrid DAC which consists of the capacitor and the resistor DACs is proposed, where the resistor DAC has little impact on the area, 6%. On-chip logic calibrates errors of the DAC in the individual channels and the channel-to-channel gain error and offset. The ADC achieves 61.8 dB peak SNDR and 78.8 dB peak SFDR at 80-MS/s and consumes 10.7 mW (6.8 mW, excluding a reference voltage generator). Over 60 dB SNDR is achieved among all measured chips.