Verification of timing constraints for fine-grain pipelined asynchronous data-path circuits

摘要

Fine-grain pipelining is a method for concealing the overhead of idle phase in dual-rail encoded, 4-phase protocol asynchronous circuits. However, new timing constraints also emerge doe to this optimization. In this manuscript, these constraints are examined for verifiability in local and global levels. A tool for automatic verification of these constraints is implemented and layout results for various data-path circuits are given.