Optimization of device parameters for ferroelectric-gate FETs using SrBi{sub}2Ta{sub}2O{sub}9 and SrTa{sub}2O{sub}6/SiON buffer layer

摘要

Ferroelectric-gate FETs are very promising to nonvolatile memory applications. In this paper, to improve electrical properties, Pt/SrBi{sub}2Ta{sub}2O{sub}9/Pt/SrTa{sub}2O{sub}6/SiON/Si MFMIS (metal-ferroelectric-metal-insulator-semiconductor)-FETs have been fabricated varying device parameters such as thicknesses of ferroelectric and buffer layers, and an area ratio between ferroelectric capacitor and floating gate. We demonstrate MFMIS-FETs which can operate at as low as 3.5V and have good data retention characteristics by optimizing the device parameters.