Built-In Self Test (BIST) techniques perform test pattern generation and response verification operations on-chip. In Arithmetic BIST, modules that commonly exist in datapaths (accumulators, counters, etc.) are utilized to perform the above-mentioned operations. In order to detect faults that occur into current CMOS circuits, two-pattern tests are required. Furthermore, delay testing, commonly used to assure correct temporal circuit operation at clock speed requires two-pattern tests. In this paper a novel two-pattern test generator for Arithmetic BIST is presented. Its hardware implementation compares favorably to the techniques that have been presented in the literature. Application of the proposed scheme for the two-pattern testing of ROM modules revealed that the testing of small-to-medium size ROMs is completed within reasonable time and with negligible hardware overhead.
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