A method to identify target crosstalk-induced delay faults in sequential circuits

摘要

In this paper, we describe a method for identifying the set of crosstalk-induced delay faults which may need to be tested in synchronous sequential circuits. Our method classifies the pairs of aggressor and victim lines using topological information and timing information, and deduces the number of faults that need to be tested in a sequential circuit. In order to reduce the number of target fautls, we try to intorduce the layout information such as circuit levle. Experimental results for ISCAS'89 and ITC'99 benchmark circuits show that the lists of the target faults obtained by the proposed method are sufficiently smaller than the sets of all possible combinations of faults.